Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition
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2021-02-21
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Abstract
In this paper, we extend the application of the Quasi-Static Memdiode model to the realistic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) intended for large dataset pattern recognition. By considering ex-situ training and the classification of
the hand-written characters of the MNIST database, we evaluate the degradation of the inference
accuracy due to the interconnection resistances for MLPs involving up to three hidden neural layers.
Two approaches to reduce the impact of the line resistance are considered and implemented in our
simulations, they are the inclusion of an iterative calibration algorithm and the partitioning of the
synaptic layers into smaller blocks. The obtained results indicate that MLPs are more sensitive to
the line resistance effect than SLPs and that partitioning is the most effective way to minimize the
impact of high line resistance values
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