Desempeño del método de análisis transitorio en la detección de fallas paramétricas en circuitos integrados.
Date
2016-04-01
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Abstract
En este trabajo se evalúa la capacidad de la estrategia de test denominada Metodología de
Análisis de Respuesta Transitoria (TRAM1
) para discriminar entre circuitos dentro y fuera de
especificaciones. Con este propósito se adopta una vista a nivel comportamiento, definiendo
una falla como un incumplimiento de alguna de las especificaciones. Si bien esta estrategia de
test ha sido estudiada por varios autores, este trabajo se enfoca en la utilización de modelos
de simulación más precisos que evitan hacer suposiciones de comportamientos ideales. Para
las evaluaciones se ha adoptado un filtro de segundo orden en la topología de variables de es-
tados, el cual ha sido diseñado totalmente a medida (full custom) en una tecnología comercial
CMOS de 500 nm. Se adopta una metodología de evaluación que inyecta desviaciones alea-
torias en los parámetros circuitales como un medio para generar una población de circuitos
con diferentes proporciones de buenos y malos. Esta población se expone posteriormente al
test para evaluar su eficiencia.
This paper evaluates the capacity of the test strategy named Transient Response Analysis Method (TRAM) to detect manufactured circuits that fall inside or outside its specifications. With this purpose, a behavioral level approach is adopted, defining a fault as the inability to comply with any of the specifications. Although this strategy has been addressed by other authors, this article focuses on the implementation of more precise simulation models to avoid the assumption of ideal components. A state variable, second order filter was implemented in a 500 nm CMOS technology following a full-custom flow, and adopted as circuit under test. To perform the evaluation, random deviations are injected to the circuit parameters, in order to create populations with different amounts of faulty and non faulty circuits. The test strategy is applied to these populations in order to evaluate its efficiency.
This paper evaluates the capacity of the test strategy named Transient Response Analysis Method (TRAM) to detect manufactured circuits that fall inside or outside its specifications. With this purpose, a behavioral level approach is adopted, defining a fault as the inability to comply with any of the specifications. Although this strategy has been addressed by other authors, this article focuses on the implementation of more precise simulation models to avoid the assumption of ideal components. A state variable, second order filter was implemented in a 500 nm CMOS technology following a full-custom flow, and adopted as circuit under test. To perform the evaluation, random deviations are injected to the circuit parameters, in order to create populations with different amounts of faulty and non faulty circuits. The test strategy is applied to these populations in order to evaluate its efficiency.
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Keywords
circuitos integrados analógicos, detección de fallas, tram, respuesta transitoria, cmos, analog integrated circuits, fault detection, transient response
Citation
Proyecciones, Vol. 14 No. 1
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